FIGS. 7(a) to 7(d) are cross-sectional views illustrating a production flow in a method for producing a prior art FET including a recess gate and a structure thereof. In these figures, reference numeral 1 designates a GaAs semiconductor substrate on which source and drain electrodes 2a and 2b are disposed. A photoresist 5 for forming a gate recess is formed on the substrate 1, covering the source and drain electrodes 2a and 2b and including an opening 5a for forming a gate recess. A recess 7 is formed by etching the substrate 1 through the opening 5a in the resist 5. Gate metal 8 is formed on the resist 5 by deposition. Gate metal 9 deposited in the recess 7 becomes a gate electrode. FIG. 7(d) is a cross-sectional view of the completed FET having a recess gate.
The recess type FET shown in FIG. 7(d) is conventionally produced in accordance with the following production flow. As shown in FIG. 7(a), the resist pattern 5 having an opening 5a of dimension d4 corresponding to the gate pattern is formed on the substrate 1. Then, as shown in FIG. 7(b), employing the resist 5 as a mask, a portion of the substrate 1 is removed by wet etching employing a tartaric acid series etchant or a phosphoric acid series etchant, thereby forming a recess 7. Then, as shown in FIG. 7(c), gate metal 8 is deposited in the state where the resist pattern 5 is disposed. Here, a metal pattern 9 directly formed on the substrate 1 becomes the gate electrode. Finally, the gate metal 8 and the resist films 5 are removed as shown in FIG. 7(d), thereby completing the FET.
Since the method for producing the prior art recess type FET is constituted as described above and the recess is formed by wet etching, a side portion of the recess of dimension d2 approximately equal to the depth d1 of the recess (d2=d1) is etched. Accordingly, there is a problem that the width w of the recess 7, more specifically, a distance d3 between an end part of the recess 7 and an end part of the gate electrode 9, depends on the depth d1 of the recess (d3=d2=d1, w=d4+2d3).
Therefore, in such a GaAs FET utilized in a high frequency band of several tens of GHz, when the above-described d3 is increased, the rise of the output signal against the input signal is flat, resulting in an unfavorable a transistor characteristic.